1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package having reduced stress at the interface between layers and a method for fabricating the same.
2. Description of the Related Art
Wafer level packaging techniques have been developed for chip packaging. A semiconductor wafer is usually bonded to a glass substrate with a spacing layer disposed therebetween. After a wafer level package is accomplished, a dicing step is performed between chips to divide them into individual chips.
An ordinary chip package may comprise a semiconductor substrate, a protection layer, a spacing layer and a glass substrate. There are some interfaces between them. However, the materials and their expansion coefficients of the above layers are different from each other. Thus, delamination may occur at the interface between any two adjacent layers of the semiconductor substrate, the protection layer, the spacing layers and the glass substrate. Therefore, moisture and air will penetrate into the chip package and result in poor electrical characteristics of the chip package.
A novel chip package and a fabrication method thereof are needed to address the above issues.